The invention lies in the semiconductor technology and memory technology fields. More specifically, the invention relates to a circuit configuration and a method for determining a time constant of a storage capacitor of a memory cell of a semiconductor memory.
Semiconductor memories have memory cells each comprising, for example, a storage capacitor (or memory capacitor) and a selection transistor. The time duration for storing or for reading out an information item into the memory cell is determined, inter alia, by the time constant of the storage capacitor. The time constant thereby depends on the storage capacitance of the storage capacitor and the lead resistance of the storage capacitor. In this case, the storage capacitor may be regarded as a capacitor connected up to a resistor.
The time constant or the delay time during the signal transfer of a capacitor connected up to a resistor is referred to, by way of example, as RC time constant. Inter alia, RC time constants of a memory cell of a semiconductor memory, can be determined by means of the present invention. In order to determine for example the RC time constants of a memory cell which has a trench capacitor as storage capacitor of the memory cell, it is advantageous to configure the standard process for fabricating a DRAM as closely as possible to the fabrication process used in the product, so that the arrangement for determining the RC time constant, which arrangement is fabricated as a test structure, corresponds to a memory cell arranged in the product.
By way of example, if the RC time constant of a trench capacitor is to be determined, then the capacitance C is formed to the greatest possible extent by the capacitance of the trench capacitor. The resistance R comprises, inter alia, the resistance of the conductive trench filling of the trench capacitor and also the resistance of a buried contact formed in the trench and the resistance of a selection transistor which is connected to the trench capacitor and is switched into the on state.
In order to determine the delay time of a memory cell capacitor connected up to a resistor, it is known from the prior art, for example, that a trench capacitor which deviates greatly from the round form of a bored hole and assumes a slotted form in the substrate and thus has greatly modified geometrical forms compared with a trench capacitor used in the product in a memory cell can be used for determining a delay time. What is problematic here is that a structure which deviates very greatly from a storage capacitor used in the product is used for determining a delay time. Consequently, a product-relevant measurement of the RC time constant of the storage capacitor used in the product is not reliably possible with this structure.
It is accordingly an object of the invention to provide a circuit configuration and method for determining a time constant of a storage capacitor of a memory cell of a semiconductor memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which is useful to determine the time constant of the storage capacitor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for determining a time constant of a storage capacitor of a memory cell of a semiconductor memory, comprising:
a ring oscillator, which has at least three series-connected inverters;
an interconnect, which has a first segment and a second segment and which connects up two inverters of the ring oscillator to one another;
a storage capacitor and a lead resistor, which has a first resistor terminal and a second resistor terminal, the first resistor terminal being connected to the storage capacitor and the second resistor terminal being connected to the interconnect between the first segment and the second segment;
a measuring device, which is connected up to the ring oscillator and which can be used to determine a value for the oscillation frequency of the ring oscillator, a device by which a value for the time constant of the storage capacitor can be determined on the basis of the value of the oscillation frequency.
The storage capacitor is connected via the lead resistor to the interconnect which is arranged between two inverters of the ring oscillator. This increases the total capacitance of the interconnect, as a result of which the oscillation frequency of the ring oscillator is reduced. The time constant of the storage capacitor and the lead resistor can be determined from the reduction of the oscillator frequency.
In accordance with an added feature of the invention, the measuring device comprises a frequency divider. A frequency divider has the advantage that it divides a possibly very high oscillation frequency of the ring oscillator down to a significantly lower frequency which, in a downstream circuit, on account of the lower frequency, can be determined in a simplified manner with a significantly lower outlay on apparatus.
In accordance with an additional feature of the invention, the circuit configuration further has
a second ring oscillator comprising at least three series-connected inverters to be arranged as reference resonant circuit, and
a mixer having a first mixer input, a second mixer input and a mixer output to be connected up to the ring oscillator and the second ring oscillator,
the first ring oscillator being connected to the first mixer input and the second ring oscillator being connected to the second mixer input and the mixer output being connected to the measuring device for the purpose of determining a value for the difference between a first frequency of the first ring oscillator and a second frequency of the second ring oscillator.
The mixer makes it possible to generate a signal which characterizes the difference between the frequency of the first ring oscillator and the second ring oscillator. This enables the direct determination of a differential frequency. The second ring oscillator is used as reference resonant circuit, so that it does not comprise, for example, the storage capacitors to be measured, the latter only being coupled to the interconnect in the case of the first ring oscillator.
A further refinement of the circuit configuration according to the invention provides for a transistor to be connected up in such a way that the lead resistor and the storage capacitor can be coupled to and decoupled from the interconnect by means of the transistor. The transistor enables the targeted connection of the storage capacitor to be measured, including the lead resistor. The conductivity and thus the electrical resistance of the controllable path of the transistor can be controlled via a gate terminal. If the controllable path is set such that it has a high resistance, then the storage capacitor is practically decoupled from the interconnect. By contrast, if the controllable path is set at very low impedance, then the storage capacitor is coupled to the interconnect and has an attenuating effect on the oscillation frequency of the ring oscillator.
In accordance with another feature of the invention, a multiplicity of storage capacitors of memory cells of a memory cell array of a semiconductor memory are connected up to the interconnect. This is advantageous since the storage capacitance of a storage capacitor of a semiconductor memory is usually made very small, so that the parallel coupling of a multiplicity of storage capacitors to the interconnect effects a frequency alteration of the oscillation frequency of the ring oscillator which is greater by a multiple. The frequency change of the ring oscillation which is enlarged by a multiple can be measured with lower measurement outlay, with reduced susceptibility to interference and increased precision.
A further advantageous refinement of the circuit configuration according to the invention provides for the circuit configuration to be arranged on a substrate, on which a word line for controlling the transistor and the interconnect are arranged, the word line running parallel to the interconnect at least in sections. By virtue of this routing of the interconnect to which the multiplicity of capacitors connected up to resistors is in each case connected, the time-delaying effect of the multiplicity of storage capacitors is combined with one another for influencing the oscillation frequency of a ring oscillator. By virtue of the special routing of the interconnect, a meandering structure is arranged on the substrate.
With the above and other objects in view there is also provided, in accordance with the invention, a method for determining a time constant of a storage capacitor of a memory cell of a semiconductor memory. The method has the following steps:
providing a circuit configuration which comprises a ring oscillator having at least three series-connected inverters,
which comprises an interconnect having a first segment and a second segment, the interconnect connecting up two inverters of the ring oscillator to one another,
which comprises a storage capacitor and a lead resistor, the lead resistor connecting the storage capacitor to the interconnect between the first segment and the second segment, and
which comprises a measuring device, which is connected up to the ring oscillator;
determining a value for the oscillation frequency of the ring oscillator by means of the measuring device, a value for the time constant of the storage capacitor being determined from the value for the oscillation frequency.
The method according to the invention makes it possible to determine the time constant of the storage capacitor.
A further, advantageous method step provides for
the lead resistor and the storage capacitor to be connected up to the interconnect by means of a transistor and to be able to be coupled to and decoupled from the interconnect by means of the transistor,
a first value for a first oscillation frequency of the ring oscillator being determined for the operation of the ring oscillator decoupled from the interconnect by means of the transistor, and
a second value for a second oscillation frequency of the ring oscillator being determined for the operation of the ring oscillator coupled to the interconnect by means of the transistor, and
the time constant of the storage capacitor to be determined on the basis of the first value and the second value.
A further refinement of the method according to the invention provides for
a second ring oscillator, which comprises at least three series-connected inverters to be provided as reference resonant circuit,
a mixer having a first mixer input and a second mixer input and a mixer output to be provided, the first ring oscillator being connected up to the first mixer input and the second ring oscillator being connected up to the second mixer input, and
the mixer to form a value for the difference between the first oscillation frequency of the first ring oscillation and the second oscillation frequency of the second ring oscillator and to communicate it to the measuring device, and
the time constant of the storage capacitor to be determined on the basis of the value for the difference between the frequencies.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration and a method for determining a time constant of a storage capacitor of a memory cell of a semiconductor memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.